In July 2026, Arm reported that its Neoverse server ecosystem had passed 1.5 billion cumulative cores shipped, and that the most recent 500 million of those went out in just nine months. In the same results, the company cited IDC data showing that spending on Arm-based accelerated server platforms had roughly doubled in two quarters and overtaken x86 platforms in that category.
That is a genuinely strange sentence to write about a data centre market that x86 owned almost completely fifteen years ago. Meanwhile RISC-V, an instruction set that costs nothing to use, is being designed into Nvidia’s software stack and into rack-mount servers. The architecture layer of computing, which was settled and boring for two decades, is contested again.
This article explains what an instruction set architecture actually is, why the old RISC-versus-CISC argument mostly stopped mattering, and what really separates ARM, x86 and RISC-V today — which turns out to be business models and software ecosystems far more than transistors.
What an instruction set architecture actually is
An instruction set architecture, or ISA, is the contract between software and hardware. It defines the operations a processor understands, how many registers it has, how memory addresses are formed, how the chip handles interrupts, and what byte sequences encode each instruction. Compilers target the ISA. Operating systems target the ISA. If two chips implement the same ISA, the same compiled binary runs on both.
What an ISA does not define is how the chip is built. Branch prediction, cache hierarchy, how many instructions issue per cycle, how deep the pipeline goes — all of that is microarchitecture, and it is where the actual engineering happens. Two chips implementing identical ISAs can differ in performance by more than an order of magnitude.
Keep that separation in mind, because almost every confused argument about “ARM versus x86 efficiency” collapses once you do.
CISC, RISC, and why the distinction blurred
The original split was real. CISC — complex instruction set computing — grew out of an era when memory was expensive and compilers were weak. Designers put elaborate instructions in hardware so a single instruction could do a lot of work, keeping programs small. The x86 family, which dates to Intel’s 8086 in 1978, is the last major survivor of that lineage.
RISC — reduced instruction set computing — came from 1980s research at Berkeley and Stanford. The insight was that simple, fixed-length, uniform instructions are much easier to pipeline and to execute several at a time. Compilers, which by then had improved, could stitch simple instructions together efficiently. ARM, MIPS, SPARC and POWER all came out of that tradition, and RISC-V is its direct academic descendant.
Why the argument stopped being decisive
Modern x86 chips are not really CISC machines internally. Since the mid-1990s they have decoded complex x86 instructions into simpler internal micro-operations and executed those on what is essentially a RISC-style out-of-order engine. Meanwhile ARM’s instruction set has accumulated a great deal of complexity of its own, including large vector extensions.
The most cited empirical work on this is a University of Wisconsin study, “Power Struggles: Revisiting the RISC vs. CISC Debate”, which measured ARM and x86 processors across 26 workloads and more than 20,000 data points. Its conclusion was that whether an ISA is RISC or CISC “seems irrelevant” to performance, power and energy on modern designs; what mattered was the design target — whether the team optimised for power or for performance — and the microarchitecture that followed from it.
There is a real residual difference. x86’s variable-length instruction encoding makes decoding harder, which constrains how wide the front end of the chip can practically be. Apple and Qualcomm have both exploited fixed-length ARM decoding to build unusually wide cores. But that is a design-cost advantage measured in percentages, not the sweeping efficiency law that marketing implies.
The business models, which matter more
The three architectures differ far more in how you get access to them than in what they compute.
| ARM | x86 | RISC-V | |
|---|---|---|---|
| Owner | Arm Holdings | Intel and AMD (cross-licensed) | RISC-V International, a Swiss non-profit |
| How you use it | License the ISA and/or Arm’s core designs | Buy chips; new entrants effectively excluded | Free to implement, no licence, no royalty |
| Cost | Upfront licence plus per-chip royalty | Product price only | Zero for the ISA; you pay for cores if you buy IP |
| Fragmentation risk | Low; Arm controls compliance | Very low | Real; managed through ratified profiles |
ARM: sell the blueprint, take a cut
Arm does not manufacture chips. It licenses the architecture to companies that design their own cores — Apple and Qualcomm both do this — and separately licenses ready-made core designs such as Cortex and Neoverse to companies that would rather not. Then it collects a royalty on every chip shipped.
In its quarter ending June 2026, Arm reported $1.29 billion in total revenue, split roughly between $715 million in royalties and $574 million in licensing. That is a small figure next to Intel or AMD, and it sits underneath tens of billions of dollars of downstream silicon. The leverage is enormous; the direct capture is modest. Arm has been steadily moving up the stack with pre-integrated Compute Subsystems to capture more value per chip.
x86: a duopoly nobody can join
x86 is not licensable in any practical sense. Intel owns the base architecture, AMD holds a long-standing cross-licence rooted in the 1980s and in AMD’s authorship of the 64-bit extension everyone now uses, and a small third licence sits with VIA and its Chinese affiliate Zhaoxin. No one else can legally build an x86 processor. That closure is why the architecture has been stable for decades and also why it has no answer to a competitor that gives its ISA away.
Facing pressure from ARM, Intel and AMD did something previously unimaginable and formed the x86 Ecosystem Advisory Group in October 2024, to keep the two companies’ extensions from diverging. Its first year produced agreed standards including AVX10 for vector instructions, FRED for interrupt handling, and ChkTag for memory tagging. It is a defensive move, and an honest admission that fragmentation was becoming a liability.
RISC-V: free, open, and still growing up
RISC-V is an open standard maintained by a non-profit. Anyone can implement it without paying anyone. That is genuinely disruptive for embedded controllers, accelerators and any company that wants sovereign control of its silicon roadmap, which is a large part of why adoption in China has been rapid.
The catch is fragmentation. A free, extensible ISA can splinter into dialects that share a name but not binaries. The fix is profiles: standardised bundles of mandatory features. RVA23, ratified in October 2024, is the important one. It makes the vector extension and the hypervisor extension mandatory for 64-bit application processors, which is what a distribution like Ubuntu or an Android build needs in order to ship one binary that runs everywhere. Google has made RVA23 the baseline for the Android RISC-V ABI.
Where each architecture actually wins today
Phones and laptops
ARM’s dominance in phones is total and uninteresting to argue about. The contested ground is laptops. Apple’s transition demonstrated that a well-designed ARM core can beat x86 on performance per watt in a thin chassis; the M5 Pro and M5 Max announced in March 2026 pair 18-core CPUs with up to 128GB of unified memory and 614GB/s of bandwidth on the Max.
On the Windows side, Qualcomm’s Snapdragon X2 Elite and X2 Elite Extreme reach up to 18 cores on a 3nm process, with the Extreme becoming the first ARM chip to hit 5 GHz on up to two cores, and an 80 TOPS NPU. Systems were scheduled for the first half of 2026. Qualcomm’s efficiency claims are vendor figures at normalised power, so treat them as directional.
The credible summary is that ARM laptops are now competitive rather than obviously superior. AMD and Intel have both closed much of the perf-per-watt gap since 2020.
Servers and cloud
This is where ARM’s gains are most concrete. AWS’s Graviton line, built on Arm Neoverse cores, has been deployed at enormous scale — Graviton4 uses Neoverse V2 and offers up to 30% better compute performance and 50% more cores than its predecessor. Google, Microsoft and Nvidia all now ship their own Arm server silicon.
The reason is unsexy and decisive: cloud workloads are mostly recompiled from source, so binary compatibility barely matters, and at hyperscale a 15% efficiency edge is worth billions in electricity and capital.
Embedded, accelerators and the RISC-V beachhead
RISC-V’s real volume today is in places you never see: storage controllers, radio basebands, power management blocks, security enclaves, and the small control processors buried inside larger chips. Nobody writes third-party software for those, so the ecosystem gap does not matter and the zero royalty does.
The 2026 forecast from the SHD Group, summarised by RISC-V International, projects 35.9 billion RISC-V-based SoC shipments and about $318 billion of associated revenue by 2031, with AI-focused parts making up roughly a quarter of units but around 70% of revenue. Analyst forecasts that far out should be read as direction, not prophecy.
Two 2026 developments matter more than any forecast. Nvidia said at Hot Chips 2026 that it is bringing CUDA support to RISC-V host CPUs, with RVA23 compliance among the requirements. And SiFive introduced a 2U rack-mount development server with 32 P870-D cores at 2 GHz, aimed at letting people port and validate data centre software. Both are enabling steps, not production deployments.
The software problem, which is the real problem
An ISA is worth what its software ecosystem is worth. Switching architectures means recompiling everything, and for anything you cannot recompile you need emulation.
Apple’s Rosetta 2 remains the benchmark for how to do this: fast ahead-of-time translation, invisible to most users. Apple is now retiring it. Full support ends after macOS 27, and from macOS 28 — expected in autumn 2027 — only a subset aimed at older games survives. macOS 26.4 began warning users when they launch apps that need it.
Microsoft’s equivalent is Prism, which translates x86 to Arm64 on the fly. A 2025 update added emulation of AVX, AVX2, BMI, FMA and F16C, which unblocked a category of creative and gaming software that previously refused to launch. Emulation still costs performance, and anti-cheat drivers in competitive games remain a persistent sore point.
RISC-V’s software position is the weakest of the three but improving fastest. Linux, GCC, LLVM, Go, Rust and the major runtimes all support it. Android’s RISC-V work is real. What is missing is the long tail of commercial, closed-source software — and there is no Rosetta for RISC-V.
What this means for you
If you are buying a laptop, choose on battery life, thermals and whether your specific applications have native builds — not on the architecture label. Check the two or three programs you genuinely depend on. An ARM Windows laptop is a good choice for browser, Office and video-call work, and a riskier one if you rely on niche plugins, VPN clients, or games with kernel-level anti-cheat. If you are on an Intel Mac, the Rosetta timeline is a real deadline: plan on being fully native before autumn 2027.
If you run cloud infrastructure, ARM instances usually deliver better price-performance for stateless services, web tiers and most managed databases. The work is in your build pipeline and container images, not your code. Test rather than assume — memory-bandwidth-bound and heavily vectorised workloads sometimes prefer x86.
If you are building hardware, RISC-V is already the sensible default for control processors and fixed-function blocks where you own the software. For anything that must run third-party binaries, ARM remains the pragmatic choice, and x86 the choice when compatibility with the existing Windows and enterprise Linux world is the requirement.
Frequently asked questions
Is ARM inherently more power-efficient than x86?
Not inherently, no. Peer-reviewed measurement work found the RISC-versus-CISC distinction largely irrelevant to energy once you account for design targets and microarchitecture. ARM chips are often more efficient in practice because they are usually designed by teams optimising for efficiency on leading-edge processes, not because of the instruction set.
Will RISC-V replace ARM?
Not soon, and probably not wholesale. RISC-V is displacing proprietary in-house cores and low-end microcontrollers first. Competing at the high end requires world-class core designs and a decade of software maturity. The likelier outcome is a three-way market where each architecture owns different niches.
Why can’t a startup just build an x86 chip?
Because x86 is protected by patents and by licences that Intel and AMD have no incentive to extend. Only Intel, AMD and the VIA/Zhaoxin line hold rights. This is the single clearest structural difference between x86 and the other two architectures.
Does running x86 software under emulation hurt performance much?
Yes, though far less than it used to. Expect a meaningful penalty relative to native code, varying by workload. Modern translators like Rosetta 2 and Prism cache translated code so repeated runs are faster, but anything CPU-bound will notice.
Is Apple Silicon just an ARM chip?
It implements the ARM instruction set under an architecture licence, but Apple designs the cores, the GPU, the neural engine and the memory system itself. The performance comes from Apple’s microarchitecture and packaging, not from ARM’s core designs.
Three architectures, three different bets
The clean version of this story would have one architecture winning. That is not what is happening. x86 keeps the enormous installed base of Windows software and enterprise Linux, and its owners have started cooperating to defend it. ARM has converted its phone dominance into real footholds in laptops and a genuinely strong position in cloud servers. RISC-V has taken over the parts of computing nobody markets, and is slowly assembling the standards and software needed to move upward.
For most of the last thirty years, choosing an instruction set was not a choice at all. It is one again, and the deciding factors are licensing terms, ecosystem depth and who controls your roadmap — not whether the instructions are reduced or complex.
Sources
- Arm Newsroom — Arm delivers record first-quarter for total revenue (Q1 FYE27)
- University of Wisconsin — Power Struggles: Revisiting the RISC vs. CISC Debate
- RISC-V International — Ratification of the RVA23 Profile Standard
- RISC-V International — Behind the scenes of SHD Group’s 2026 RISC-V market forecast
- AMD — AMD and Intel celebrate first anniversary of the x86 Ecosystem Advisory Group
- Intel Newsroom — Intel and AMD form x86 Ecosystem Advisory Group
- Apple Newsroom — Apple debuts M5 Pro and M5 Max
- Tom’s Hardware — Qualcomm’s Snapdragon X2 Elite Extreme and Elite chips
- Arm Newsroom — Accelerating cloud innovation with AWS Graviton4
- Chips and Cheese — Hot Chips 2026: CUDA targets RISC-V
- The Register — SiFive pushes development server to take RISC-V into the datacenter
- 9to5Mac — macOS 26.4 will notify users of Rosetta 2 discontinuation
- Neowin — Prism update unlocks AVX, AVX2 support for Windows on Arm
Image credit: Photo: Raimond Spekking — CC BY-SA 4.0 (via Wikimedia Commons)
